20.2.9 Hardware, VLSI Implementations, Embedded Processors, Sensor Processing

Moini, A.[Alireza],
Vision Chips,
KluwerOctober 1999. ISBN 0-7923-8664-7
WWW Link. smart visual sensors, are those sensors that have integrated image acquisition and parallel processing, often at the pixel level, using dedicated analog and digital circuits. BibRef 9910

Roska, T.[Tamás], Rodriguez-Vazquez, A.,
Toward visual microprocessors,
PIEEE(90), No. 7, July 2002, pp. 1244-1257.
IEEE DOI 0207
BibRef

Roska, T.[Tamás],
The analogic single-chip CNN visual supercomputer: A review,
CAIP93(813-821).
Springer DOI 9309
BibRef

Wu, B.F.[Bing-Fei], Hu, Y.Q.[Yi-Qiang],
An efficient VLSI implementation of the discrete wavelet transform using embedded instruction codes for symmetric filters,
CirSysVideo(13), No. 9, September 2003, pp. 936-943.
IEEE Abstract. 0310
BibRef

Kessal, L., Abel, N., Demigny, D.,
Real-time image processing with dynamically reconfigurable architecture,
RealTimeImg(9), No. 5, October 2003, pp. 297-313.
Elsevier DOI 0311
BibRef

Kessal, L., Demigny, D., Boudouani, N., Bourgiba, R.,
Reconfigurable Hardware for Real Time Image Processing,
ICIP00(Vol III: 110-113).
IEEE DOI 0008
BibRef

Fürtler, J.[Johannes], Mayer, K.J.[Konrad J.], Krattenthaler, W.[Werner], Bajla, I.[Ivan],
SPOT: Development tool for software pipeline optimization for VLIW-DSPs used in real-time image processing,
RealTimeImg(9), No. 6, December 2003, pp. 387-399.
Elsevier DOI 0401
BibRef

Lu, C.K., Summerfield, S.,
Design and VLSI implementation of QMF banks,
VISP(151), No. 5, October 2004, pp. 421-427.
IEEE Abstract. 0501
BibRef

Huang, C.T., Tseng, P.C., Chen, L.G.,
Generic RAM-Based Architectures for Two-Dimensional Discrete Wavelet Transform With Line-Based Method,
CirSysVideo(15), No. 7, July 2005, pp. 910-920.
IEEE DOI 0508
BibRef

Artyomov, E., Rivenson, Y., Levi, G., Yadid-Pecht, O.,
Morton (Z) Scan Based Real-Time Variable Resolution CMOS Image Sensor,
CirSysVideo(15), No. 7, July 2005, pp. 947-952.
IEEE DOI 0508
BibRef

Bishnu, A., Bhattacharya, B.B., Kundu, M.K., Murthy, C.A., Acharya, T.,
Euler vector for search and retrieval of gray-tone images,
SMC-B(35), No. 4, August 2005, pp. 801-812.
IEEE DOI 0508
BibRef
Earlier:
On-chip Computation of Euler Number of a Binary Image for Efficient Database Search,
ICIP01(III: 310-313).
IEEE DOI 0108
BibRef

Bishnu, A., Bhunre, P.K., Bhattacharya, B.B., Kundu, M.K., Murthy, C.A.,
Content Based Image Retrieval: Related Issues Using Euler Vector,
ICIP02(II: 585-588).
IEEE DOI 0210
BibRef

Bolcioni, L., Campi, F., Canegallo, R., Guerrieri, R.,
A low-power system-on-chip for the documentation of road accidents,
CirSysVideo(15), No. 11, November 2005, pp. 1493-1501.
IEEE DOI 0512
BibRef

Martina, M.[Maurizio], Masera, G.[Guido],
Mumford and Shah Functional: VLSI Analysis and Implementation,
PAMI(28), No. 3, March 2006, pp. 487-494.
IEEE DOI 0602

See also Optimal Approximations by Piecewise Smooth Functions and Variational Problems. BibRef

Reyna-Rojas, R.[Roberto], Houzet, D.[Dominique], Dragomirescu, D.[Daniela], Carlier, F.[Florent], Ouadjaout, S.[Salim],
Object Recognition System-on-Chip Using the Support Vector Machines,
JASP(2005), No. 7, 2005, pp. 993-1004.
WWW Link. 0603
BibRef

Barbaro, M.[Massimo], Raffo, L.[Luigi],
A Low-Power Integrated Smart Sensor with on-Chip Real-Time Image Processing Capabilities,
JASP(2005), No. 7, 2005, pp. 1062-1070.
WWW Link. 0603
BibRef

Kleihorst, R.P.[Richard P.], Abbo, A.A.[Anteneh A.], Choudhary, V.[Vishal], Broers, H.[Harry],
Scalable IC Platform for Smart Cameras,
JASP(2005), No. 13, 2005, pp. 2018-2025.
WWW Link. 0603
BibRef

Kleihorst, R.P.[Richard P.], Abbo, A.A.[Anteneh A.], Schueler, B.[Ben], Danilin, A.[Alexander],
Camera Mote with a High-Performance Parallel Processor for Real-Time Frame-Based Video Processing,
AVSBS07(69-74).
IEEE DOI 0709
BibRef
And: ICDSC07(109-116).
IEEE DOI 0709
BibRef

Fischer, V.[Viktor], Lukac, R.[Rastislav], Martin, K.[Karl],
Cost-Effective Video Filtering Solution for Real-Time Vision Systems,
JASP(2005), No. 13, 2005, pp. 2026-2042.
WWW Link. 0603
BibRef

Wang, D., Yu, N., Gao, Y., Zhang, R.,
Effective correlation vector quantisation algorithm and its VLSI architecture,
VISP(153), No. 6, December 2006, pp. 735-738.
DOI Link 0702
BibRef

Bensaali, F., Amira, A.,
Field programmable gate array based parallel matrix multiplier for 3D affine transformations,
VISP(153), No. 6, December 2006, pp. 739-746.
DOI Link 0702
BibRef

Dang, P.[Philip],
VLSI architecture for real-time image and video processing systems,
RealTimeIP(1), No. 1, October 2006, pp. 57-62.
Springer DOI 0001
BibRef

Saponara, S.[Sergio], Fanucci, L.[Luca], Marsi, S.[Stefano], Ramponi, G.[Giovanni],
Algorithmic and architectural design for real-time and power-efficient Retinex image/video processing,
RealTimeIP(1), No. 4, July 2007, pp. 267-283.
Springer DOI 0707
BibRef

Saponara, S.[Sergio], Casula, M.[Michele], Fanucci, L.[Luca],
ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing,
RealTimeIP(3), No. 3, September 2008, pp. xx-yy.
Springer DOI 0804
BibRef

Marsi, S.[Stefano], Saponara, S.[Sergio],
Integrated video motion estimator with Retinex-like pre-processing for robust motion analysis in automotive scenarios: algorithmic and real-time architecture design,
RealTimeIP(5), No. 4, December 2010, pp. 275-289.
WWW Link. 1101
BibRef

Saponara, S.[Sergio],
Real-time and low-power processing of 3D direct/inverse discrete cosine transform for low-complexity video codec,
RealTimeIP(7), No. 1, March 2012, pp. 43-53.
WWW Link. 1202
BibRef

Banerjee, S., Evans, B.L.,
In-Camera Automation of Photographic Composition Rules,
IP(16), No. 7, July 2007, pp. 1807-1820.
IEEE DOI 0707
BibRef

Cheng, C.C., Huang, C.T., Chen, C.Y., Lian, C.J., Chen, L.G.,
On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform,
CirSysVideo(17), No. 7, July 2007, pp. 814-822.
IEEE DOI 0707
BibRef

Chen, J.C., Chien, S.Y.,
CRISP: Coarse-Grained Reconfigurable Image Stream Processor for Digital Still Cameras and Camcorders,
CirSysVideo(18), No. 9, September 2008, pp. 1223-1236.
IEEE DOI 0810
BibRef

Hiromoto, M.[Masayuki], Sugano, H.[Hiroki], Miyamoto, R.[Ryusuke],
Partially Parallel Architecture for AdaBoost-Based Detection with Haar-Like Features,
CirSysVideo(19), No. 1, January 2009, pp. 41-52.
IEEE DOI 0902

See also Object Detection Based on Image Blur Using Spatial-Domain Filtering with Haar-Like Features. BibRef

Hiromoto, M.[Masayuki], Nakahara, K.[Kentaro], Sugano, H.[Hiroki], Nakamura, Y.[Yukihiro], Miyamoto, R.[Ryusuke],
A Specialized Processor Suitable for AdaBoost-Based Detection with Haar-like Features,
EmbedCV07(1-8).
IEEE DOI 0706
BibRef

Razeghi, M., Hoffman, D., Nguyen, B.M., Delaunay, P.Y., Huang, E.K., Tidrow, M.Z., Nathan, V.,
Recent Advances in LWIR Type-II InAs/GaSb Superlattice Photodetectors and Focal Plane Arrays at the Center for Quantum Devices,
PIEEE(97), No. 6, June 2009, pp. 1056-1066.
IEEE DOI 0905
BibRef

Gao, C., Lu, S.L.L., Suh, T., Lim, H.,
Field programmable gate array-ased haar classifier for accelerating face detection algorithm,
IET-IPR(4), No. 3, June 2010, pp. 184-194.
DOI Link 1006
BibRef

Kisacanin, B.[Branislav], Nikolic, Z.[Zoran],
Algorithmic and software techniques for embedded vision on programmable processors,
SP:IC(25), No. 5, June 2010, pp. 352-362.
Elsevier DOI 1007
Real-time; Embedded; Vision; Programmable; DSP BibRef

Karthigaikumar, P., Baskaran, K.,
Partially Pipelined VLSI Implementation Of Blowfish Encryption/decryption Algorithm,
IJIG(10), No. 3, July 2010, pp. 327-341.
DOI Link 1003
BibRef

Sugano, H.[Hiroki], Miyamoto, R.[Ryusuke],
Highly optimized implementation of OpenCV for the Cell Broadband Engine,
CVIU(114), No. 11, November 2010, pp. 1273-1281.
Elsevier DOI 1011
BibRef
Earlier:
A Real-Time Object Recognition System on Cell Broadband Engine,
PSIVT07(932-943).
Springer DOI 0712
Embedded processor (Sony playstation). 18fps for 8 targets. Image processing; OpenCV; Parallel implementation; Cell Broadband Engine BibRef

Jordan, H.[Harald], van Dyck, W.[Walter], Smodic, R.[Rene],
A co-processed contour tracing algorithm for a smart camera,
RealTimeIP(6), No. 1, March 2011, pp. 23-31.
WWW Link. 1103
BibRef

Tseng, Y.C., Hsu, P.H., Chang, T.S.,
A 124 Mpixels/s VLSI Design for Histogram-Based Joint Bilateral Filtering,
IP(20), No. 11, November 2011, pp. 3231-3241.
IEEE DOI 1110
BibRef

Chen, S.L., Huang, H.Y., Luo, C.H.,
A Low-Cost High-Quality Adaptive Scalar for Real-Time Multimedia Applications,
CirSysVideo(21), No. 11, November 2011, pp. 1600-1611.
IEEE DOI 1111
BibRef

Chen, S.L., Huang, H.Y., Luo, C.H.,
Time Multiplexed VLSI Architecture for Real-Time Barrel Distortion Correction in Video-Endoscopic Images,
CirSysVideo(21), No. 11, November 2011, pp. 1612-1621.
IEEE DOI 1111
BibRef

Chen, S.L.,
VLSI Implementation of an Adaptive Edge-Enhanced Image Scalar for Real-Time Multimedia Applications,
CirSysVideo(23), No. 9, 2013, pp. 1510-1522.
IEEE DOI 1309
Algorithm design and analysis BibRef

Chen, S.L.[Shih-Lun], Ma, E.D.[En-Di],
VLSI Implementation of an Adaptive Edge-Enhanced Color Interpolation Processor for Real-Time Video Applications,
CirSysVideo(24), No. 11, November 2014, pp. 1982-1991.
IEEE DOI 1411
VLSI BibRef

Al Najjar, M.[Mayssaa], Karlapudi, S.[Swetha], Bayoumi, M.[Magdy],
Memory-Efficient Architecture for Hysteresis Thresholding and Object Feature Extraction,
IP(20), No. 12, December 2011, pp. 3566-3579.
IEEE DOI 1112
BibRef
And:
High-performance asic architecture for hysteresis thresholding and component feature extraction in limited-resource applications,
ICIP11(1061-1064).
IEEE DOI 1201
hysteresis thresholding avoided in streaming processing. BibRef

Huang, C.C.[Chien-Chuan], Chen, P.Y.[Pei-Yin], Ma, C.H.[Ching-Hsuan],
A Novel Interpolation Chip for Real-Time Multimedia Applications,
CirSysVideo(22), No. 10, October 2012, pp. 1512-1525.
IEEE DOI 1210
BibRef

Park, J.S., Kim, H.E., Kim, L.S.,
A 182 mW 94.3 f/s in Full HD Pattern-Matching Based Image Recognition Accelerator for an Embedded Vision System in 0.13-mu-m CMOS Technology,
CirSysVideo(23), No. 5, May 2013, pp. 832-845.
IEEE DOI 1305
BibRef

Chen, J.[Jienan], Hu, J.[Jianhao],
High Throughput Stochastic Log-MAP Turbo-Decoder Based on Low Bits Computation,
SPLetters(20), No. 11, 2013, pp. 1098-1101.
IEEE DOI 1310
CMOS integrated circuits BibRef

Granados, S.[Sara], Barranco, F.[Francisco], Mota, S.[Sonia], Díaz, J.[Javier], Ros, E.[Eduardo],
On-chip semidense representation map for dense visual features driven by attention processes,
RealTimeIP(9), No. 1, March 2014, pp. 171-185.
Springer DOI 1403
condense features to allow for processing on chip BibRef

Wang, J.H.[Jian-Hui], Zhong, S.[Sheng], Yan, L.[Luxin], Cao, Z.G.[Zhi-Guo],
An Embedded System-on-Chip Architecture for Real-time Visual Detection and Matching,
CirSysVideo(24), No. 3, March 2014, pp. 525-538.
IEEE DOI 1404
computational complexity BibRef

Jiang, J., Li, X., Zhang, G.,
SIFT Hardware Implementation for Real-Time Image Feature Extraction,
CirSysVideo(24), No. 7, July 2014, pp. 1209-1220.
IEEE DOI 1407
Computer architecture BibRef

Madanayake, A.[Arjuna], Wimalagunarathne…, R.[Randeel],
VLSI architecture for 4-D depth filtering,
SIViP(9), No. 4, May 2015, pp. 809-818.
WWW Link. 1504
BibRef

Schlessman, J.[Jason], Wolf, M.[Marilyn],
Tailoring Design for Embedded Computer Vision Applications,
Computer(48), No. 5, May 2015, pp. 58-62.
IEEE DOI 1506
Algorithm design and analysis BibRef

Belyaev, E., Liu, K., Gabbouj, M., Li, Y.,
An Efficient Adaptive Binary Range Coder and Its VLSI Architecture,
CirSysVideo(25), No. 8, August 2015, pp. 1435-1446.
IEEE DOI 1508
Encoding BibRef

Belyaev, E., Forchhammer, S., Liu, K.,
An Adaptive Multialphabet Arithmetic Coding Based on Generalized Virtual Sliding Window,
SPLetters(24), No. 7, July 2017, pp. 1034-1038.
IEEE DOI 1706
adaptive codes, arithmetic codes, probability, adaptive multialphabet arithmetic coding, compression performance, generalized virtual sliding window, multialphabet multiplication-free adaptive arithmetic coder, multiplication-free binary arithmetic coders, probability adaptation speed, probability estimation, Decoding, Encoding, Estimation, Indexes, Radiation detectors, Registers, Signal processing algorithms, Multialphabet arithmetic coding, probability, estimation BibRef

Zhou, T., Dong, T., Su, Y., He, Y.,
A CMOS Readout With High-Precision and Low-Temperature-Coefficient Background Current Skimming for Infrared Focal Plane Array,
CirSysVideo(25), No. 8, August 2015, pp. 1447-1455.
IEEE DOI 1508
Arrays BibRef

Maggiani, L., Bourrasset, C., Petracca, M., Berry, F., Pagano, P., Salvadori, C.,
HOG-Dot: A Parallel Kernel-Based Gradient Extraction for Embedded Image Processing,
SPLetters(22), No. 11, November 2015, pp. 2132-2136.
IEEE DOI 1509
feature extraction BibRef

Fu, X.N.[Xiao-Ning], Wang, J.[Jie],
Algorithm and code optimizations for real-time passive ranging by imaging detection on single DSP,
SIViP(9), No. 6, September 2015, pp. 1377-1386.
Springer DOI 1509
Real time implementation of SIFT matching. BibRef

Pedre, S.[Sol], Krajník, T.[Tomáš], Todorovich, E.[Elías], Borensztejn, P.[Patricia],
Accelerating embedded image processing for real time: a case study,
RealTimeIP(11), No. 2, February 2016, pp. 349-374.
Springer DOI 1602
BibRef

Monroe, D.[Don],
Silicon Photonics: Ready to Go the Distance?,
CACM(59), No. 5, May 2016, pp. 26-28.
DOI Link 1605
CMOS for optical circuits BibRef

Zhu, W., Liu, L., Jiang, G., Yin, S., Wei, S.,
A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator,
CirSysVideo(26), No. 8, August 2016, pp. 1532-1543.
IEEE DOI 1609
CMOS integrated circuits BibRef

Sérot, J.[Jocelyn], Berry, F.[François], Bourrasset, C.[Cédric],
High-level dataflow programming for real-time image processing on smart cameras,
RealTimeIP(12), No. 4, December 2016, pp. 635-647.
Springer DOI 1612
BibRef

Pelissier, F.[Frantz], Chenini, H.[Hanen], Berry, F.[François], Landrault, A.[Alexis], Derutin, J.P.[Jean-Pierre],
Embedded multi-processor system-on-programmable chip for smart camera pose estimation using nonlinear optimization methods,
RealTimeIP(12), No. 4, December 2016, pp. 663-679.
Springer DOI 1612
BibRef

Müller, J.[Jens], Müller, J.[Jan], Tetzlaff, R.[Ronald],
NEROvideo: a general-purpose CNN-UM video processing system,
RealTimeIP(12), No. 4, December 2016, pp. 763-774.
Springer DOI 1612
BibRef

Ye, L.H.[Li-Hua], Yao, K.[Keqi], Hang, J.J.[Jian-Jun], Tu, P.P.[Ping-Ping], Cui, Y.P.[Yi-Ping],
A hardware solution for real-time image acquisition systems based on GigE camera,
RealTimeIP(12), No. 4, December 2016, pp. 827-834.
Springer DOI 1612
More the issue of how much processing is required to get the image and what to do about that. BibRef

Meyer-Baese, U.[Uwe], Meyer-Baese, A.[Anke], González, D.[Diego], Botella, G.[Guillermo], García, C.[Carlos], Prieto-Matías, M.[Manuel],
Code obfuscation using very long identifiers for FFT motion estimation models in embedded processors,
RealTimeIP(11), No. 4, April 2016, pp. 817-827.
Springer DOI 1604
Protecting the code on devices. BibRef

Ackerman, E.,
Motion-planning chip speeds robots,
Spectrum(54), No. 1, January 2017, pp. 9-10.
IEEE DOI 1702
grippers BibRef

Ratnayake, K.[Kumara], Amer, A.[Aishy],
Embedded architecture for noise-adaptive video object detection using parameter-compressed background modeling,
RealTimeIP(13), No. 2, June 2017, pp. 397-414.
WWW Link. 1708
BibRef

Saussard, R.[Romain], Bouzid, B.[Boubker], Vasiliu, M.[Marius], Reynaud, R.[Roger],
A novel global methodology to analyze the embeddability of real-time image processing algorithms,
RealTimeIP(14), No. 3, March 2018, pp. 565-583.
Springer DOI 1804
BibRef

George, A.D., Wilson, C.M.,
Onboard Processing With Hybrid and Reconfigurable Computing on Small Satellites,
PIEEE(106), No. 3, March 2018, pp. 458-470.
IEEE DOI 1804
aerospace computing, artificial satellites, microcontrollers, parallel processing, space vehicle electronics, space radiation BibRef

Yang, J., Yang, Y., Chen, Z., Liu, L., Liu, J., Wu, N.,
A Heterogeneous Parallel Processor for High-Speed Vision Chip,
CirSysVideo(28), No. 3, March 2018, pp. 746-758.
IEEE DOI 1804
feature extraction, microprocessor chips, parallel processing, self-organising feature maps, MPU controls, vision chip BibRef

Aguilar-González, A.[Abiel], Arias-Estrada, M.[Miguel], Berry, F.[François],
Robust feature extraction algorithm suitable for real-time embedded applications,
RealTimeIP(14), No. 3, March 2018, pp. 647-665.
Springer DOI 1804
Includes pseudo-code implementation. BibRef

Hartmann, C.[Christian], Fey, D.[Dietmar],
An extended analysis of memory hierarchies for efficient implementations of image processing applications,
RealTimeIP(14), No. 3, March 2018, pp. 713-728.
Springer DOI 1804
BibRef

Chen, Q., Sun, H., Zheng, N.,
Worst Case Driven Display Frame Compression for Energy-Efficient Ultra-HD Display Processing,
MultMed(20), No. 5, May 2018, pp. 1113-1125.
IEEE DOI 1805
Bandwidth, Encoding, Energy consumption, Image coding, Memory management, Streaming media, Throughput, very large scale integration (VLSI) architecture BibRef

Bartovský, J.[Jan], Dokládal, P.[Petr], Faessel, M.[Matthieu], Dokladalova, E.[Eva], Bilodeau, M.[Michel],
Morphological co-processing unit for embedded devices,
RealTimeIP(15), No. 4, December 2018, pp. 775-786.
Springer DOI
WWW Link. 1812
BibRef

Mefenza, M.[Michael], Yonga, F.[Franck], Bobda, C.[Christophe],
Component interconnect and data access interface for embedded vision applications,
RealTimeIP(15), No. 4, December 2018, pp. 759-773.
WWW Link. 1812
BibRef

Perez-Neira, A.I., Vazquez, M.A., Shankar, M.R.B., Maleki, S., Chatzinotas, S.,
Signal Processing for High-Throughput Satellites: Challenges in new interference-limited scenarios,
SPMag(36), No. 4, July 2019, pp. 112-131.
IEEE DOI 1907
Satellites, Satellite broadcasting, Orbits, Signal processing, Throughput, Wireless communication, Broadband communication BibRef

Saponara, S.[Sergio],
Hardware accelerator IP cores for real time Radar and camera-based ADAS,
RealTimeIP(16), No. 5, October 2019, pp. 1493-1510.
WWW Link. 1911
BibRef

Athreyas, N.[Nihar], Gupta, D.[Dev], Gupta, J.[Jai],
Analog signal processing solution for machine vision applications,
RealTimeIP(16), No. 5, October 2019, pp. 1607-1628.
WWW Link. 1911
BibRef

Díaz, M.[María], Guerra, R.[Raúl], Horstrand, P.[Pablo], López, S.[Sebastián], López, J.F.[José F.], Sarmiento, R.[Roberto],
Towards the Concurrent Execution of Multiple Hyperspectral Imaging Applications by Means of Computationally Simple Operations,
RS(12), No. 8, 2020, pp. xx-yy.
DOI Link 2004
BibRef

Virtanen, J.P.[Juho-Pekka], Daniel, S.[Sylvie], Turppa, T.[Tuomas], Zhu, L.[Lingli], Julin, A.[Arttu], Hyyppä, H.[Hannu], Hyyppä, J.[Juha],
Interactive dense point clouds in a game engine,
PandRS(163), 2020, pp. 375-389.
Elsevier DOI 2005
Hardware processing for real-time RGB-D processing. Point cloud, Game engine, VR BibRef

Li, J.C.[Jin-Cheng], Deng, G.Q.[Guo-Qing], Zhang, W.[Wen], Zhang, C.F.[Chao-Fan], Wang, F.[Fan], Liu, Y.[Yong],
Realization of CUDA-based real-time multi-camera visual SLAM in embedded systems,
RealTimeIP(17), No. 3, June 2020, pp. 713-727.
Springer DOI 2006
BibRef

Abid, N.[Nesrine], Loukil, K.[Kais], Ouni, T.[Tarek], Ayedi, W.[Walid], Ammari, A.C.[Ahmed Chiheb], Abid, M.[Mohamed],
An improvement of multi-scale covariance descriptor for embedded system,
RealTimeIP(17), No. 3, June 2020, pp. 419-435.
Springer DOI 2006
BibRef

Batta, K.N.S., Chakrabarti, I.,
VLSI Architecture for Enhanced Approximate Message Passing Algorithm,
CirSysVideo(30), No. 9, September 2020, pp. 3253-3267.
IEEE DOI 2009
Approximation algorithms, Matching pursuit algorithms, Signal processing algorithms, Computer architecture, approximate message passing (AMP) BibRef

Lou, Y., Duan, L.Y., Luo, Y., Chen, Z., Liu, T., Wang, S., Gao, W.,
Towards Efficient Front-End Visual Sensing for Digital Retina: A Model-Centric Paradigm,
MultMed(22), No. 11, November 2020, pp. 3002-3013.
IEEE DOI 2010
Biological system modeling, Retina, Adaptation models, Visualization, Brain modeling, Computational modeling, Sensors, visual sensing BibRef

Mohanty, B.K.,
Parallel VLSI Architecture for Approximate Computation of Discrete Hadamard Transform,
CirSysVideo(30), No. 12, December 2020, pp. 4944-4952.
IEEE DOI 2012
DH-HEMTs, Transforms, Finite wordlength effects, Computer architecture, Adders, Very large scale integration, VLSI BibRef

Park, J.H.[Ji Hyun], Inamori, T.[Takaya], Hamaguchi, R.[Ryuhei], Otsuki, K.[Kensuke], Kim, J.E.[Jung Eun], Yamaoka, K.[Kazutaka],
RGB Image Prioritization Using Convolutional Neural Network on a Microprocessor for Nanosatellites,
RS(12), No. 23, 2020, pp. xx-yy.
DOI Link 2012
BibRef

Anbaran, A.M.[Alireza Mohammadi], Torkzadeh, P.[Pooya], Ebrahimpour, R.[Reza], Bagheri, N.[Nasour],
Modification and hardware implementation of cortex-like object recognition model,
IET-IPR(14), No. 14, December 2020, pp. 3490-3498.
DOI Link 2012
BibRef

Wei, L.Y.[Lin-Yu], Cai, J.P.[Jue-Ping], Wang, W.Z.[Wu-Zhuang],
ATA: Attentional Non-Linear Activation Function Approximation for VLSI-Based Neural Networks,
SPLetters(28), 2021, pp. 793-797.
IEEE DOI 2105
Hardware, Fitting, Table lookup, Approximation methods, Sensitivity, Feature extraction, Function approximation, Neural networks, hardware implementation BibRef

Ziaja, M.[Maciej], Bosowski, P.[Piotr], Myller, M.[Michal], Gajoch, G.[Grzegorz], Gumiela, M.[Michal], Protich, J.[Jennifer], Borda, K.[Katherine], Jayaraman, D.[Dhivya], Dividino, R.[Renata], Nalepa, J.[Jakub],
Benchmarking Deep Learning for On-Board Space Applications,
RS(13), No. 19, 2021, pp. xx-yy.
DOI Link 2110
BibRef

Lin, C.H.[Chia-Hsiang], Lin, T.H.[Tzu-Hsuan],
All-Addition Hyperspectral Compressed Sensing for Metasurface-Driven Miniaturized Satellite,
GeoRS(60), 2022, pp. 1-15.
IEEE DOI 2112
Decoding, Hyperspectral imaging, Small satellites, Sensors, Encoding, Tensors, TV, Convex optimization, self-similarity BibRef

Hu, Y.[Yang], Wen, G.H.[Gui-Hua], Luo, M.[Mingnan], Dai, D.[Dan], Cao, W.M.[Wen-Ming], Yu, Z.W.[Zhi-Wen], Hall, W.[Wendy],
Inner-Imaging Networks: Put Lenses Into Convolutional Structure,
Cyber(52), No. 8, August 2022, pp. 8547-8560.
IEEE DOI 2208
Convolution, Shape, Computational modeling, Lenses, Redundancy, Computer science, Channelwise attention, inner-imaging (InI) BibRef

Zhang, Z.Q.[Zhi-Qi], Qu, Z.[Zhuo], Liu, S.Y.[Si-Yuan], Li, D.H.[De-Hua], Cao, J.S.[Jin-Shan], Xie, G.Q.[Guang-Qi],
Expandable On-Board Real-Time Edge Computing Architecture for Luojia3 Intelligent Remote Sensing Satellite,
RS(14), No. 15, 2022, pp. xx-yy.
DOI Link 2208
BibRef

Lee, H.C.[Hsu-Chi], Lu, Y.C.[Yun-Chih], Lin, Y.C.[Yu-Chen], Lai, W.L.[Wei-Lin], Hsieh, H.Y.[Hsiang-Yuan], Jaw, B.Y.[Boy-Yiing], Chuang, C.T.[Chin-Tang], Chen, Y.C.[Yung-Chih], Chen, Y.J.E.[Yi-Jan Emery],
A High Voltage Driving Chiplet in Standard 0.18-µm CMOS for Micro-Pixelated LED Displays Integrated With LTPS TFTs,
CirSysVideo(32), No. 10, October 2022, pp. 7204-7211.
IEEE DOI 2210
Light emitting diodes, Thin film transistors, Backplanes, Routing, Active matrix organic light emitting diodes, Threshold voltage, level shifter BibRef

Song, R.B.[Rui-Bing], Huang, K.J.[Ke-Jie], Wang, Z.S.[Zong-Sheng], Shen, H.B.[Hai-Bin],
A Reconfigurable Convolution-in-Pixel CMOS Image Sensor Architecture,
CirSysVideo(32), No. 10, October 2022, pp. 7212-7225.
IEEE DOI 2210
Sensors, Convolutional neural networks, Convolution, Transistors, Capacitors, Sensor arrays, Processing-in-pixel, visual perception, CMOS image sensor BibRef

Wang, X.[Xiang], Cui, X.W.[Xiao-Wei], Liu, G.[Gang], Lu, M.Q.[Ming-Quan],
Designing the Signal Quality Monitoring Algorithm Based on Chip Domain Observables for BDS B1C/B2a Signals under the Requirements of DFMC SBAS,
RS(15), No. 4, 2023, pp. xx-yy.
DOI Link 2303
BibRef

He, C.Y.[Chang-Yuan], Dong, Y.F.[Yun-Feng], Li, H.J.[Hong-Jue], Liew, Y.J.[Ying-Jia],
Reasoning-Based Scheduling Method for Agile Earth Observation Satellite with Multi-Subsystem Coupling,
RS(15), No. 6, 2023, pp. 1577.
DOI Link 2304
Processing on satellite. BibRef

Kwak, M.H.[Min Ho], Kim, Y.[Youngwoo], Lee, K.[Kangin], Choi, J.Y.[Jae Young],
Convolution Block Feature Addition Module (CBFAM) for Lightweight and Fast Object Detection on Non-GPU Devices,
IEICE(E106-D), No. 5, May 2023, pp. 1106-1110.
WWW Link. 2305
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Lv, H.S.[Hu-Shan], Li, Y.R.[Yong-Rui], Xie, Y.Z.[Yi-Zhuang], Qiao, T.T.[Ting-Ting],
An Efficient On-Chip Data Storage and Exchange Engine for Spaceborne SAR System,
RS(15), No. 11, 2023, pp. 2885.
DOI Link 2306
BibRef

Hu, X.[Xiao], Jiao, Z.T.[Zi-Teng], Kocher, A.[Ayden], Wu, Z.Y.[Zhen-Yu], Liu, J.J.[Jun-Jie], Davis, J.C.[James C.], Thiruvathukal, G.K.[George K.], Lu, Y.H.[Yung-Hsiang],
Evolution of Winning Solutions in the 2021 Low-Power Computer Vision Challenge,
Computer(56), No. 8, August 2023, pp. 28-37.
IEEE DOI 2308
Power demand, Guidelines BibRef

Langer, D.D.[Dennis D.], Orlandic, M.[Milica], Bakken, S.[Sivert], Birkeland, R.[Roger], Garrett, J.L.[Joseph L.], Johansen, T.A.[Tor A.], Sørensen, A.J.[Asgeir J.],
Robust and Reconfigurable On-Board Processing for a Hyperspectral Imaging Small Satellite,
RS(15), No. 15, 2023, pp. xx-yy.
DOI Link 2308
BibRef

Zhao, Y.X.[Yu-Xin], Feng, H.[Hancong], Jiang, K.[Kaili], Tang, B.[Bin],
Information Fusion for Radar Signal Sorting with the Distributed Reconnaissance Receivers,
RS(15), No. 15, 2023, pp. xx-yy.
DOI Link 2308
Do analysis at sensor. BibRef

Maheshwari, S.[Sidharth], Rahman, T.[Tousif], Shafik, R.[Rishad], Yakovlev, A.[Alex], Rafiev, A.[Ashur], Jiao, L.[Lei], Granmo, O.C.[Ole-Christoffer],
REDRESS: Generating Compressed Models for Edge Inference Using Tsetlin Machines,
PAMI(45), No. 9, September 2023, pp. 11152-11168.
IEEE DOI 2309
BibRef

Zhou, Q.H.[Qi-Hua], Guo, S.[Song], Pan, J.[Jun], Liang, J.C.[Jia-Cheng], Guo, J.[Jingcai], Xu, Z.[Zhenda], Zhou, J.[Jingren],
PASS: Patch Automatic Skip Scheme for Efficient On-Device Video Perception,
PAMI(46), No. 5, May 2024, pp. 3938-3954.
IEEE DOI 2404
Task analysis, Logic gates, Streaming media, Feature extraction, Streams, Computational modeling, Termination of employment, visual analytics BibRef

Liu, Q.[Qiang], Guo, F.[Fucheng], Xiong, K.[Kunlai], Liu, Z.M.[Zhang-Meng], Hu, W.D.[Wei-Dong],
LPI Sequences Optimization Method against Summation Detector Based on FFT Filter Bank,
RS(16), No. 11, 2024, pp. 2021.
DOI Link 2406
BibRef

Zhang, N.[Ning], Chen, H.[He], Chen, L.[Liang], Wang, J.[Jue], Wang, G.Q.[Guo-Qing], Liu, W.C.[Wen-Chao],
Q-A2NN: Quantized All-Adder Neural Networks for Onboard Remote Sensing Scene Classification,
RS(16), No. 13, 2024, pp. 2403.
DOI Link 2407
BibRef

Dastagir, M.B.A.[Muhammad Bilal Akram], Han, D.S.[Dong-Soo],
Towards Hybrid Quantum-Classical Deep Learning Architecture for Indoor-Outdoor Detection Using QCNN-LSTM and Cluster State Signal Processing,
SPLetters(31), 2024, pp. 2945-2949.
IEEE DOI 2411
Qubit, Computational modeling, Logic gates, Integrated circuit modeling, Quantum circuit, Deep learning, quantum pool circuit BibRef

Guo, Y.H.[Yan-Hui], Luo, F.Z.[Fang-Zhou], We, X.L.[Xiao-Lin],
Learning Degradation-Independent Representations for Camera ISP Pipelines,
CVPR24(25774-25783)
IEEE DOI 2410
Degradation, Instance segmentation, Scalability, Pipelines, Noise, Artificial neural networks, Self-supervised learning, Image Restoration BibRef

Prabhune, O.[Omkar], Chen, T.[Tianen], Kim, Y.[Younghyun],
Content-aware Input Scaling and Deep Learning Computation Offloading for Low-Latency Embedded Vision,
ECVW24(2218-2226)
IEEE DOI 2410
Deep learning, Training, Radio frequency, Visualization, Accuracy, Machine vision, Face recognition, deep learning, efficient ML, low-power ML BibRef

Aydin, A.[Asude], Gehrig, M.[Mathias], Gehrig, D.[Daniel], Scaramuzza, D.[Davide],
A Hybrid ANN-SNN Architecture for Low-Power and Low-Latency Visual Perception,
AIS24(5701-5711)
IEEE DOI Code:
WWW Link. 2410
Accuracy, Pose estimation, Computer architecture, Spiking neural networks, Predictive models, ANN-SNN hybrid model BibRef

Tang, Y.J.[Yu-Jin], Dong, P.[Peijie], Tang, Z.[Zhenheng], Chu, X.W.[Xiao-Wen], Liang, J.W.[Jun-Wei],
VMRNN: Integrating Vision Mamba and LSTM for Efficient and Accurate Spatiotemporal Forecasting,
Precognition24(5663-5673)
IEEE DOI Code:
WWW Link. 2410
Recurrent neural networks, Accuracy, Computational modeling, Microprocessors, Computer architecture, Predictive models, State Space Model BibRef

Park, S.[Seongmin], Lee, M.[Minjae], Choi, J.[Junwon], Choi, J.[Jungwook],
Selectively Dilated Convolution for Accuracy-Preserving Sparse Pillar-based Embedded 3D Object Detection,
ECV24(8104-8113)
IEEE DOI 2410
Point cloud compression, Accuracy, Convolution, Computational modeling, Redundancy, Random access memory BibRef

Sarkar, S.[Sreetama], Kundu, S.[Souvik], Zheng, K.[Kai], Beerel, P.A.[Peter A.],
Block Selective Reprogramming for On-device Training of Vision Transformers,
ECV24(8094-8103)
IEEE DOI Code:
WWW Link. 2410
Training, Costs, Quantization (signal), Codes, Computational modeling, vision transformer, on-device training, token pruning BibRef

Mosleh, A.[Ali], Tahaei, M.S.[Marzieh S.], Clark, J.J.[James J.], Nia, V.P.[Vahid Partovi],
Towards Low-Cost Learning-based Camera ISP via Unrolled Optimization,
CRV23(9-18)
IEEE DOI 2406
ISP: image signal processor. Training, Learning systems, Computational modeling, Pipelines, Noise reduction, Memory management, Robot sensing systems, ISP, Image Degradation BibRef

Liu, Y.W.[Yin-Wei], Jiang, Y.C.[Yu-Chen],
The Optimizated CIELAB Colour Model For All-Analog Photoelectronic High Speed Vision-Task Chip (ACCEL) by Creative Computing Approach,
IoTDesign24(708-715)
IEEE DOI 2404
Solid modeling, Visualization, Computational modeling, Hidden Markov models, Color, Virtual reality, Bayes methods, computer photons chip BibRef

Budhkar, P.[Prerna], Rao, N.[Navneet], Sundaram, J.[Jainaveen], Karnik, T.[Tanay],
CPU Microarchitectural Performance Analysis of SVT-AV1 Encoder,
ICIP23(3045-3049)
IEEE DOI 2312
BibRef

Fosco, C.L.[Camilo L.], Jin, S.Y.[Sou-Young], Josephs, E.[Emilie], Oliva, A.[Aude],
Leveraging Temporal Context in Low Representational Power Regimes,
CVPR23(10693-10703)
IEEE DOI 2309

WWW Link. BibRef

Alhejaili, R.[Rawwad], Alfarraj, M.[Motaz], Luqman, H.[Hamzah], Al-Shaikhi, A.[Ali],
Recursions Are All You Need: Towards Efficient Deep Unfolding Networks,
ECV23(4705-4714)
IEEE DOI 2309
BibRef

Ro, Y.[Yeonju], Xu, C.[Cong], Ciborowska, A.[Agnieszka], Bhattacharya, S.[Suparna], Li, F.[Frankie], Foltin, M.[Martin],
Dataset Efficient Training with Model Ensembling,
ECV23(4700-4704)
IEEE DOI 2309
BibRef

Li, Z.H.[Zhang-Heng], Gong, Y.[Yu], Zhang, Z.Y.[Zhen-Yu], Xue, X.Y.[Xing-Yun], Chen, T.L.[Tian-Long], Liang, Y.[Yi], Yuan, B.[Bo], Wang, Z.Y.[Zhang-Yang],
Accelerable Lottery Tickets with the Mixed-Precision Quantization,
ECV23(4604-4612)
IEEE DOI 2309
BibRef

Yang, Y.D.[Yue-Dong], Li, G.[Guihong], Marculescu, R.[Radu],
Efficient On-Device Training via Gradient Filtering,
CVPR23(3811-3820)
IEEE DOI 2309
BibRef

Datta, G.[Gourav], Yin, Z.H.[Zi-Han], Jacob, A.P.[Ajey P.], Jaiswal, A.R.[Akhilesh R.], Beerel, P.A.[Peter A.],
Towards Energy-efficient Hyperspectral Image Processing Inside Camera Pixels,
DSC22(303-316).
Springer DOI 2304
BibRef

Zheng, J.[Jiesi], Fan, Z.H.[Zhi-Hao], Wu, X.[Xun], Wu, Y.[Yaqi], Zhang, F.[Feng],
Residual Feature Distillation Channel Spatial Attention Network for ISP on Smartphone,
AIM22(635-650).
Springer DOI 2304
BibRef

Örnhag, M.V.[Marcus Valtonen], Güler, P.[Püren], Knyaginin, D.[Dmitry], Borg, M.[Mattias],
Accelerating AI using next-generation hardware: Possibilities and challenges with analog in-memory computing,
VAQuality23(488-496)
IEEE DOI 2302
Performance evaluation, Phase change materials, Semantic segmentation, Scalability, Memristors, In-memory computing BibRef

Abbasi, S.[Saad], Wong, A.[Alexander], Shafiee, M.J.[Mohammad Javad],
MAPLE: Microprocessor A Priori for Latency Estimation,
ECV22(2746-2755)
IEEE DOI 2210
Measurement, Training, Performance evaluation, Deep learning, Microprocessors, Neural networks, Graphics processing units BibRef

Liang, F.[Feng], Chin, T.W.[Ting-Wu], Zhou, Y.[Yang], Marculescu, D.[Diana],
ANT: Adapt Network Across Time for Efficient Video Processing,
ECV22(2602-2607)
IEEE DOI 2210
Training, Adaptive systems, Redundancy, Semantics, Switches, Streaming media, Logic gates BibRef

Sadiq, S.[Sulaiman], Hare, J.[Jonathon], Maji, P.[Partha], Craske, S.[Simon], Merrett, G.V.[Geoff V.],
TinyOps: ImageNet Scale Deep Learning on Microcontrollers,
ECV22(2701-2705)
IEEE DOI 2210
Deep learning, Microcontrollers, Memory management, Internet of Things BibRef

Dey, S.[Swarnava], Dasgupta, P.[Pallab], Chakrabarti, P.P.[Partha P],
SymDNN: Simple & Effective Adversarial Robustness for Embedded Systems,
EVW22(3598-3608)
IEEE DOI 2210
Adaptation models, Visualization, Embedded systems, Computational modeling, Symbols, Transforms BibRef

Kandaswamy, I.[Indhumathi], Farkya, S.[Saurabh], Daniels, Z.[Zachary], van der Wal, G.[Gooitzen], Raghavan, A.[Aswin], Zhang, Y.Z.[Yu-Zheng], Hu, J.[Jun], Lomnitz, M.[Michael], Isnardi, M.[Michael], Zhang, D.[David], Piacentino, M.[Michael],
Real-time Hyper-Dimensional Reconfiguration at the Edge using Hardware Accelerators,
EVW22(3609-3617)
IEEE DOI 2210
Quantization (signal), Power measurement, System performance, Software algorithms, Feature extraction, Real-time systems BibRef

Mantowsky, S.[Sven], Heuer, F.[Falk], Bukhari, S.S.[Syed Saqib], Keckeisen, M.[Michael], Schneider, G.[Georg],
ProAI: An Efficient Embedded AI Hardware for Automotive Applications: A Benchmark Study,
ERCVAD21(972-978)
IEEE DOI 2112
Performance evaluation, Deep learning, Technological innovation, Power demand, Computer architecture, Benchmark testing, Safety BibRef

Heuer, F.[Falk], Mantowsky, S.[Sven], Bukhari, S.S.[Syed Saqib], Schneider, G.[Georg],
MultiTask-CenterNet (MCN): Efficient and Diverse Multitask Learning using an Anchor Free Approach,
ERCVAD21(997-1005)
IEEE DOI 2112
Training, Head, Semantics, Pose estimation, Computer architecture BibRef

Xu, S.[Sheng], Zhao, J.[Junhe], Lü, J.[Jinhu], Zhang, B.C.[Bao-Chang], Han, S.[Shumin], Doermann, D.[David],
Layer-wise Searching for 1-bit Detectors,
CVPR21(5678-5687)
IEEE DOI 2111
Performance evaluation, Training, Satellite broadcasting, Detectors, Object detection BibRef

Kovács, B.[Bertalan], Henriksen, A.D.[Anders D.], Stets, J.D.[Jonathan Dyssel], Nalpantidis, L.[Lazaros],
Object Detection on TPU Accelerated Embedded Devices,
CVS21(82-92).
Springer DOI 2109
BibRef

Chen, T.W.[Tse-Wei], Wang, D.Y.[De-Yu], Tao, W.[Wei], Wen, D.C.[Dong-Chao], Yin, L.X.[Ling-Xiao], Ito, T.[Tadayuki], Osa, K.[Kinya], Kato, M.[Masami],
CASSOD-Net: Cascaded and Separable Structures of Dilated Convolution for Embedded Vision Systems and Applications,
EVW21(3176-3184)
IEEE DOI 2109
Image segmentation, Machine vision, Hardware, Face detection, Convolutional neural networks BibRef

Kucik, A.S.[Andrzej S.], Meoni, G.[Gabriele],
Investigating Spiking Neural Networks for Energy-Efficient On-Board AI Applications. A Case Study in Land Cover and Land Use Classification,
AI4Space21(2020-2030)
IEEE DOI 2109
Potential energy, Energy consumption, Satellites, Quantization (signal), Data preprocessing, Pipelines, Energy efficiency BibRef

Namiki, S.[Shigeaki], Yokoyama, K.[Keiko], Yachida, S.[Shoji], Shibata, T.[Takashi], Miyano, H.[Hiroyoshi], Ishikawa, M.[Masatoshi],
Online Object Recognition Using CNN-based Algorithm on High-speed Camera Imaging: Framework for fast and robust high-speed camera object recognition based on population data cleansing and data ensemble,
ICPR21(2025-2032)
IEEE DOI 2105
Image recognition, Sociology, Object detection, Cameras, Real-time systems, Robustness, Image classification BibRef

Li, Y.[Yue], Ding, W.R.[Wen-Rui], Zhu, Y.J.[Yan-Jun], Huang, Y.J.[Yuan-Jun], Jiang, Y.L.[Ya-Long], Zhang, B.C.[Bao-Chang],
Cam-Net: Compressed Attentive Multi-Granularity Network For Dynamic Scene Classification,
ICIP20(668-672)
IEEE DOI 2011
Computational modeling, Feature extraction, Task analysis, Benchmark testing, Dynamic scheduling, Image reconstruction, dynamic scene classification BibRef

Zhang, T., Jiao, J., Zhang, C., Zhao, Y., Wang, C., Cui, W., Chen, X.,
M-Sosanet: An Efficient Convolution Network Backbone For Embedding Devices,
ICIP20(1721-1725)
IEEE DOI 2011
lightweight, Aggregation, Score BibRef

Dokic, K.[Kristian],
Microcontrollers on the Edge: Is ESP32 with Camera Ready for Machine Learning?,
ICISP20(213-220).
Springer DOI 2009
BibRef

Farcas, A., Li, G., Bhardwaj, K., Marculescu, R.,
A Hardware Prototype Targeting Distributed Deep Learning for On-device Inference,
LPCV20(1600-1601)
IEEE DOI 2008
Pattern recognition BibRef

Han, K.[Kai], Wang, Y.H.[Yun-He], Tian, Q.[Qi], Guo, J.Y.[Jian-Yuan], Xu, C.J.[Chun-Jing], Xu, C.[Chang],
GhostNet: More Features From Cheap Operations,
CVPR20(1577-1586)
IEEE DOI 2008
Deploy on embedded devices. Convolution, Computational modeling, Computer architecture, Redundancy, Biological neural networks, Convolutional neural networks BibRef

Simpson, B., Lubana, E., Liu, Y., Dick, R.,
Intelligent Scene Caching to Improve Accuracy for Energy-Constrained Embedded Vision,
EDLCV20(3114-3122)
IEEE DOI 2008
Cameras, Energy consumption, Energy resolution, Image resolution, Streaming media, Servers, Object detection BibRef

Bose, L., Dudek, P., Chen, J., Carey, S., Mayol-Cuevas, W.,
A Camera That CNNs: Towards Embedded Neural Networks on Pixel Processor Arrays,
ICCV19(1335-1344)
IEEE DOI 2004
array signal processing, convolutional neural nets, field programmable gate arrays, image capture, image resolution, Sensor arrays BibRef

Jose, G., Kumar, A., Kruthiventi, S.S.S., Saha, S., Muralidhara, H.,
Real-Time Object Detection On Low Power Embedded Platforms,
LPCV19(2485-2492)
IEEE DOI 2004
computational complexity, data compression, embedded systems, learning (artificial intelligence), neural nets, ADAS BibRef

Zemlyanikin, M., Smorkalov, A., Khanova, T., Petrovicheva, A., Serebryakov, G.,
512KiB RAM Is Enough! Live Camera Face Recognition DNN on MCU,
LPCV19(2493-2500)
IEEE DOI 2004
cameras, face recognition, learning (artificial intelligence), microcontrollers, neural nets, reduced instruction set computing, face recognition BibRef

Cai, H., Wang, T., Wu, Z., Wang, K., Lin, J., Han, S.,
On-Device Image Classification with Proxyless Neural Architecture Search and Quantization-Aware Fine-Tuning,
LPCV19(2509-2513)
IEEE DOI 2004
gradient methods, image classification, learning (artificial intelligence), neural nets, optimisation, Quantization Aware Fine tuning BibRef

van Beeck, K.[Kristof], Tuytelaars, T.[Tinne], Scarramuza, D.[Davide], Goedemé, T.[Toon],
Real-Time Embedded Computer Vision on UAVs,
CVUAV18(II:3-10).
Springer DOI 1905
BibRef

Fu, Y.M.[Yan-Mei], Wu, F.G.[Feng-Ge], Zhao, J.S.[Jun-Suo],
Context-Aware and Depthwise-based Detection on Orbit for Remote Sensing Image,
ICPR18(1725-1730)
IEEE DOI 1812
Filter useless data before download. Feature extraction, Remote sensing, Convolution, Object detection, Orbits, Satellites, Context modeling BibRef

Gao, H., Tao, W., Wen, D., Chen, T., Osa, K., Kato, M.,
IFQ-Net: Integrated Fixed-Point Quantization Networks for Embedded Vision,
ECVW18(720-7208)
IEEE DOI 1812
Quantization (signal), Convolution, Face, Computational modeling, Task analysis, Detectors, Runtime BibRef

Singh, B.[Bharat], Li, H.D.[Heng-Duo], Sharma, A.[Abhishek], Davis, L.S.[Larry S.],
R-FCN-3000 at 30fps: Decoupling Detection and Classification,
CVPR18(1081-1090)
IEEE DOI 1812
Detectors, Object detection, Training, Proposals, Convolution, Computer architecture, Dogs BibRef

Rajagopal, V.[Vasanthakumar], Ramasamy, C.K.[Chandra Kumar], Vishnoi, A.[Ashok], Gadde, R.N.[Raj Narayana], Miniskar, N.R.[Narasinga Rao], Pasupuleti, S.K.[Sirish Kumar],
Accurate and Efficient Fixed Point Inference for Deep Neural Networks,
ICIP18(1847-1851)
IEEE DOI 1809
Quantization (signal), Kernel, Mathematical model, Open area test sites, Neural networks, Training, Bandwidth, Inference BibRef

El Alaoui, M., Farah, F., El Khadiri, K., Qjidaa, H., Aarab, A., El Alami, R., Lakhassassi, A.,
Analysis and design of dickson charge pump for EEPROM in 180nm CMOS technology,
ISCV18(1-5)
IEEE DOI 1807
CMOS memory circuits, EPROM, charge pump circuits, clocks, integrated circuit design, private key cryptography, Pre-Regulator BibRef

Cyganek, B.,
Software framework for tensor stream processing on embedded vision platforms,
AVSS17(1-6)
IEEE DOI 1806
embedded systems, image colour analysis, video signal processing, abrupt signal change detection, Tensile stress BibRef

Ayala, D., Chávez, D.,
Notice of Remova:l Low cost embedded vision system for location and tracking of a color object,
3DTV-CON17(1-5)
IEEE DOI 1804
Paper removed from conference. BibRef

Mathew, M., Desappan, K., Swami, P.K., Nagori, S.,
Sparse, Quantized, Full Frame CNN for Low Power Embedded Devices,
ECVW17(328-336)
IEEE DOI 1709
Complexity theory, Digital signal processing, Quantization (signal), Streaming media, Tensile stress, Training, Tuning BibRef

Roy, F., Mamdy, B., Ahmed, N., Tournier, A., Lu, G.N.,
Development of small-sized pixel structures for high-resolution CMOS image sensors,
ICIVC17(494-500)
IEEE DOI 1708
Crosstalk, Dark current, Diffusion tensor imaging, Optical crosstalk, Passivation, Photodiodes, Transistors, 2T pixel architecture, MOS capacitor deep trench isolation (CDTI), P-type and N-type pixel options, back-side illumination (BSI), single-transistor pixel, vertical, photodiode BibRef

Hadj Salem, K., Kieffer, Y., Mancini, S.,
Memory management in embedded vision systems: Optimization problems and solution methods,
DASIP16(200-207)
IEEE DOI 1704
computer vision BibRef

Xia, T.[Tian], Rihani, M.A.F., Prévotet, J.C., Nouvel, F.,
Demo: Ker-ONE: Embedded virtualization approach with dynamic reconfigurable accelerators management,
DASIP16(225-226)
IEEE DOI 1704
embedded systems BibRef

Sau, C., Fanni, T., Meloni, P., Raffo, L., Pelcat, M., Palumbo, F.,
Demo: Reconfigurable Platform Composer Tool,
DASIP16(245-246)
IEEE DOI 1704
embedded systems BibRef

Basterretxea, K., Martinez-Corral, U., Finker, R., del Campo, I.,
ELM-based hyperspectral imagery processor for onboard real-time classification,
DASIP16(43-50)
IEEE DOI 1704
geophysical image processing BibRef

Tan, B., Biglari-Abhari, M., Salcic, Z.,
A system-level security approach for heterogeneous MPSoCs,
DASIP16(74-81)
IEEE DOI 1704
embedded systems BibRef

Desoli, G.[Giuseppe], Tomaselli, V.[Valeria], Plebani, E.[Emanuele], Urlini, G.[Giulio], Pau, D.[Danilo], d'Alto, V.[Viviana], Majo, T.[Tommaso], de Ambroggi, F.[Fabio], Boesch, T.[Thomas], Singh, S.P.[Surinder-Pal], Guidetti, E.[Elio], Chawla, N.[Nitin],
The Orlando Project: A 28 nm FD-SOI Low Memory Embedded Neural Network ASIC,
ACIVS16(217-227).
Springer DOI 1611
BibRef

Werner, S., Stiehle, B., Becker, J.,
Evaluation of analog and digital signal processing on PSoC architecture with DCT as use case: Comparison of an analog and software based implementation of the digital cosine transform on a Programmable System on Chip,
DASIP15(1-6)
IEEE DOI 1605
digital signal processing chips BibRef

MATIP: A dynamic hardware task integration platform for Multiprocessing Reconfigurable System on Chip,
DASIP15(1-6)
IEEE DOI 1605
distributed memory systems BibRef

Cyriac, P.[Praveen], Kane, D.[David], Bertalmio, M.[Marcelo],
Perceptual Dynamic Range for In-Camera Image Processing,
BMVC15(xx-yy).
DOI Link 1601
BibRef

Fresse, V., Ge, Z.W.[Zhi-Wei], Tan, J.Y.[Jun-Yan], Rousseau, F.,
Case study: Deployment of the 2D NoC on 3D for the generation of large emulation platforms,
IPTA12(435-441)
IEEE DOI 1503
field programmable gate arrays Network-On-Chip architecture. BibRef

Ekstrand, F.[Fredrik], Ahlberg, C.[Carl], Ekström, M.[Mikael], Spampinato, G.[Giacomo],
Towards an Embedded Real-Time High Resolution Vision System,
ISVC14(II: 541-550).
Springer DOI 1501
BibRef

Shoaib, S.[Saad], Hafiz, R.[Rehan], Shafique, M.[Muhammad],
Hardware/Software Co-design of Embedded Real-Time KD-Tree Based Feature Matching Systems,
ISVC14(II: 936-945).
Springer DOI 1501
BibRef

Zhou, G.[Guyue], Liu, A.[Ang], Yang, K.[Kang], Wang, T.[Tao], Li, Z.X.[Ze-Xiang],
An Embedded Solution to Visual Mapping for Consumer Drones,
ECVW14(670-675)
IEEE DOI 1409
embedded vision; sensor fusion; visual mapping BibRef

Zhang, B.[Buyue], Appia, V.[Vikram], Pekkucuksen, I.[Ibrahim], Liu, Y.C.[Yu-Cheng], Batur, A.U.[Aziz Umit], Shastry, P.[Pavan], Liu, S.[Stanley], Sivasankaran, S.J.[Shi-Ju], Chitnis, K.[Kedar],
A Surround View Camera Solution for Embedded Systems,
ECVW14(676-681)
IEEE DOI 1409
ADAS BibRef

Thieling, L.[Lothar], Schuer, A.[Andre], Hartung, G.[Georg], Buchel, G.[Gregor],
Embedded image processing system for cloud-based applications,
WSSIP14(163-166) 1406
Cameras BibRef

Hamilton, L., Parker, D., Yu, C., Indyk, P.,
Focal plane array folding for efficient information extraction and tracking,
AIPR12(1-6)
IEEE DOI 1307
analogue-digital conversion BibRef

Rajesvari, R., Manoj, G., Ponrani, M.A.[M. Angelin], Joy, M.A.[Merin Annie],
IP core based architecture of telecommand System-on-Chip (SoC) for spacecraft applications,
ICSIPR13(163-168).
IEEE DOI 1304
BibRef

Ring, M.[Matthias], Jensen, U.[Ulf], Kugler, P.[Patrick], Eskofier, B.[Bjoern],
Software-based performance and complexity analysis for the design of embedded classification systems,
ICPR12(2266-2269).
WWW Link. 1302
BibRef

Luxenburger, A.[Andreas], Zimmer, H.[Henning], Gwosdek, P.[Pascal], Weickert, J.[Joachim],
Fast PDE-Based Image Analysis in Your Pocket,
SSVM11(544-555).
Springer DOI 1201
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Chong, W.[Wang], Hong, Z.[Zheng], Zhen, L.[Li],
Hardware/software co-design of embedded image processing system using systemc modeling platform,
IASP11(524-528).
IEEE DOI 1112
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Sardar, S.[Santu], Tewari, G.[Gaurav], Babu, K.A.,
A hardware/software co-design model for face recognition using Cognimem Neural Network chip,
ICIIP11(1-6).
IEEE DOI 1112
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Padfield, D.[Dirk],
The magic sigma,
CVPR11(129-136).
IEEE DOI 1106
Embedded processors with integer computations, how to do Gaussians. BibRef

Bailey, D.G.[Donald G.],
Adapting algorithms for hardware implementation,
ECVW11(177-184).
IEEE DOI 1106
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Kraft, M.[Marek], Fularz, M.[Michal], Kasinski, A.[Andrzej],
System on Chip Coprocessors for High Speed Image Feature Detection and Matching,
ACIVS11(599-610).
Springer DOI 1108
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Frias-Velazquez, A.[Andres], Philips, W.[Wilfried],
Bit-plane stack filter algorithm for focal plane processors,
ICIP10(3741-3744).
IEEE DOI 1009
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Zezza, S.[Simone], Masera, G.[Guido], Nooshabadi, S.[Saeid],
A feasible VLSI engine for soft-input-soft-output for joint source channel codes,
ICIP09(2669-2672).
IEEE DOI 0911
BibRef

Xu, Y.[Yong], Zhao, F.[Fei], Xu, Y.B.[Yong-Bin], Guan, Y.[Yu],
A Novel Chip Design of Chopper-Stabilized Rail-to-Rail Operational Amplifier,
CISP09(1-4).
IEEE DOI 0910
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Caulfield, J.T., McCarley, P.L., Elliott, J., Massie, M.A.,
Bandwidth efficient sensor architectures with feature extraction,
AIPR08(1-5).
IEEE DOI 0810
Focal Plane Array processors. BibRef

Cook, S., Harsanyi, J.,
Onboard processor for compressing HSI data,
AIPR02(200-204).
IEEE DOI 0210
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Wall, G., Iqbal, F., Isaacs, J., Liu, X.W.[Xiu-Wen], Foo, S.,
Real time texture classification using field programmable gate arrays,
AIPR04(130-135).
IEEE DOI 0410
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Li, H.Y.[Hui-Ya], Hwang, W.J.[Wen-Jyi], Hsu, C.C.[Chih-Chieh], Hung, C.L.[Chia-Lung],
Efficient K-Means VLSI Architecture for Vector Quantization,
SCIA09(440-449).
Springer DOI 0906
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Atani, R.E.[R. Ebrahimi], Mirzakuchaki, S., Atani, S.E.[S. Ebrahimi],
Design and Implementation of an Image CoProcessor,
ICISP08(498-507).
Springer DOI 0807
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Diaz, I., Heijligers, M., Kleihorst, R.P., Danilin, A.,
An Embedded Low Power High Efficient Object Tracker for Surveillance Systems,
ICDSC07(372-378).
IEEE DOI 0709
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Litzenberger, M., Belbachir, A.N., Schon, P., Posch, C.,
Embedded Smart Camera for High Speed Vision,
ICDSC07(81-86).
IEEE DOI 0709
BibRef

Leon-Salas, W.D., Velipasalar, S., Schemm, N., Balkir, S.,
A Low-Cost, Tiled Embedded Smart Camera System for Computer Vision Applications,
ICDSC07(125-131).
IEEE DOI 0709
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Cornelis, N.[Nico], Van Gool, L.J.[Luc J.],
Fast scale invariant feature detection and matching on programmable graphics hardware,
CVGPU08(1-8).
IEEE DOI 0806
BibRef

Wang, B.J.[Bang-Ju], Zhang, H.G.[Huan-Guo], Wang, Z.Y.[Zhang-Yi], Wang, Y.H.[Yu-Hua],
Speeding Up Scalar Multiplication Using a New Signed Binary Representation for Integers,
MCAM07(277-285).
Springer DOI 0706
BibRef

Lai, M.C.[Ming-Che], Guo, J.J.[Jian-Jun], Lv, Y.S.[Ya-Suai], Dai, K.[Kui], Wang, Z.Y.[Zhi-Ying],
The Research of an Embedded Processor Element for Multimedia Domain,
MCAM07(267-276).
Springer DOI 0706
BibRef

Gabriel, R.C., Gomes, J., de Mello, M.J.C., Haas, H.L., Petraglia, A.,
New Error Sensitivity Model for the Analog Hardware Implementation of Inner Products,
ICIP06(3333-3336).
IEEE DOI 0610
BibRef

Rowe, A., Goode, A.G., Goel, D., and Nourbakhsh, I.,
CMUcam3: An Open Programmable Embedded Vision Sensor,
CMU-RI-TR-07-13, May, 2007.
WWW Link. BibRef 0705

Rowe, A., Rosenberg, C., Nourbakhsh, I.,
A Second Generation Low Cost Embedded Color Vision System,
EmbedCV05(III: 136-136).
IEEE DOI 0507
BibRef

Gong, M.L.[Ming-Lun], Langille, A.[Aaron], Gong, M.W.[Ming-Wei],
Real-Time Image Processing Using Graphics Hardware: A Performance Study,
ICIAR05(1217-1225).
Springer DOI 0509
BibRef

Jodoin, P.M.[Pierre-Marc], Mignotte, M.[Max], St-Amour, J.F.[Jean-François],
Markovian Energy-Based Computer Vision Algorithms on Graphics Hardware,
CIAP05(592-603).
Springer DOI 0509
BibRef

Kisacanin, B.[Branislav],
Integral Image Optimizations for Embedded Vision Applications,
Southwest08(181-184).
IEEE DOI 0803
BibRef
Earlier:
Examples of Low-Level Computer Vision on Media Processors,
EmbedCV05(III: 135-135).
IEEE DOI 0507
BibRef

Stein, G.P., Rushinek, E., Hayun, G., Shashua, A.,
A Computer Vision System on a Chip: A case study from the automotive domain,
EmbedCV05(III: 130-130).
IEEE DOI 0507
BibRef

Bertalmio, M., Fort, P., Sanchez-Crespo, D.,
Real-time, accurate depth of field using anisotropic diffusion and programmable graphics cards,
3DPVT04(767-773).
IEEE DOI 0412
BibRef

Elouardi, A., Bouaziz, S., Dupret, A., Klein, J.O., Reynaud, R.,
On chip vision system architecture using a CMOS retina,
IVS04(206-211).
IEEE DOI 0411
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Woetzel, J., Koch, R.,
Multi-camera real-time depth estimation with discontinuity handling on PC graphics hardware,
ICPR04(I: 741-744).
IEEE DOI 0409
BibRef

Aziz, M., Boussakta, S., McLernon, D.C.,
Three-dimensional digital filtering algorithm for parallel DSP implementation,
ICIP03(II: 579-582).
IEEE DOI 0312
BibRef

Laffely, A., Liang, J.[Jian], Tessier, R., Burleson, W.,
Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores,
ICIP03(III: 105-108).
IEEE DOI 0312
BibRef

Michell, J.A., Ruiz, G.A., Buron, A.M.,
Parallel-pipelined architecture for 2-D ICT VLSI implementation,
ICIP03(III: 89-92).
IEEE DOI 0312
BibRef

Lv, T., Ozer, B., Wolf, W.,
Exploiting parallelism in media processing using VLIW processor,
ICIP03(III: 97-100).
IEEE DOI 0312
BibRef

Lee, S.W.[Seong-Whan], Lee, S.W.[Sang-Woong], Jung, H.C.[Ho-Choul],
Real-Time Implementation of Face Recognition Algorithms on DSP Chip,
AVBPA03(294-301).
Springer DOI 0310
BibRef

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Video Analysis using the Acadia I(TM) Single-Chip Vision System,
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A Floating Gate CMOS Euclidean Distance Calculator and Its Application to Hand-written Digit Recognition,
ICIP01(III: 350-353).
IEEE DOI 0108
BibRef

McCanny, P., Masud, S., McCanny, J.,
An Efficient Architecture for the 2-d Biorthogonal Discrete Wavelet Transform,
ICIP01(III: 314-317).
IEEE DOI 0108
BibRef

Sudharsanan, S., Sriram, P., Frederickson, H., Gulati, A.,
Image and Video Processing Using MAJC 5200,
ICIP00(Vol III: 122-125).
IEEE DOI 0008
BibRef

Ooi, R., Hamamoto, T., Naemura, T., Aizawa, K.,
Pixel Independent Random Access Image Sensor for Real Time Image-based Rendering System,
ICIP01(II: 193-196).
IEEE DOI 0108
BibRef

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Real-Time Image Processing by Using Image Compression Sensor,
ICIP99(III:935-939).
IEEE DOI BibRef 9900

Peng, W.S.[Wen-Shiaw], Lee, C.Y.[Chen-Yi],
An Efficient VLSI Architecture for Separable 2-D Discrete Wavelet Transform,
ICIP99(II:754-758).
IEEE DOI BibRef 9900

Sousa, L.[Leonel],
Applying Conditional Processing to Design Low-Power Array Processors for Motion Estimation,
ICIP99(II:769-773).
IEEE DOI BibRef 9900

Ishikawa, M.[Masatoshi],
1ms VLSI Vision Chip System and Its Applications,
AFGR98(214-219).
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Sicard, G., Bouvier, G., Lelah, A.,
A Light Adaptive 4000 Pixels Analog Silicon Retina for Edge Extraction and Motion Detection,
MVA98(xx-yy). BibRef 9800

Benedetti, A.[Arrigo], Perona, P.[Pietro],
Real-Time 2-D Feature Detection on a Reconfigurable Computer,
CVPR98(586-593).
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Redford, J.,
A three Giga-op DSP chip for image processing,
ICIP98(III: 981-984).
IEEE DOI 9810
BibRef

Muramatsu, S., Kobayashi, Y., Araoka, M., Naoi, S., Kaneta, T., Hirose, K., Onizawa, S.,
Image processing LSI 'ISP-IV' based on local parallel architecture and its applications,
ICIP98(III: 1000-1004).
IEEE DOI 9810
BibRef

Gokstorp, M., Forchheimer, R.,
Smart vision sensors,
ICIP98(I: 479-482).
IEEE DOI 9810
BibRef

Spirig, T., Seitz, P., Vietze, O., Heitger, F., Kubler, O.,
Real-time 2D feature detection with low-level image processing algorithms on smart CCD/CMOS image sensors,
ICIP96(II: 1043-1046).
IEEE DOI 9610
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Chen, C.C.[Chih-Chin], Jen, C.W.[Chein-Wei],
A programmable concurrent video signal processor,
ICIP96(II: 1039-1042).
IEEE DOI 9610
BibRef

Sorel, Y.,
Real-time embedded image processing applications using the A3 methodology,
ICIP96(II: 145-148).
IEEE DOI 9610
BibRef

Ker, J.S.[Jar-Shone], Kuo, Y.H.[Yau-Hwang], Liu, B.D.[Bin-Da],
Design of a color reproduction neural network chip with on-chip learning capability,
ICIP96(II: 1023-1026).
IEEE DOI 9610
BibRef

Chen, C.L.[Chao-Lieh], Lee, C.S.[Chang-Shing], Kuo, Y.H.[Yau-Hwang],
Design of high speed weighted fuzzy mean filters with generic LR fuzzy cells,
ICIP96(II: 1027-1030).
IEEE DOI 9610
BibRef

Dallaire, S., Poussart, D., Tremblay, M.,
Low Level Segmentation Using CMOS Smart Hexagonal Image Sensor,
CAMP95(xx). BibRef 9500

Pechanek, G.G., Stojancic, M., Vassiliadis, S., Glossner, C.J.,
MFAST: a single chip highly parallel image processing architecture,
ICIP95(I: 69-72).
IEEE DOI 9510
BibRef

Muller, S.,
A new programmable VLSI architecture for histogram and statistics computation in different windows,
ICIP95(I: 73-76).
IEEE DOI 9510
BibRef

Potkonjak, M.,
Discrete-relaxation-based heuristic techniques for video algorithm/architecture matching and system level transformations,
ICIP95(I: 77-80).
IEEE DOI 9510
BibRef

Olstad, B., Steen, E., Halaas, A.,
Image filtering techniques and VLSI architectures for efficient data extraction in shell rendering,
ICIP95(II: 113-116).
IEEE DOI 9510
BibRef

Ranganathan, N., Venygopal, S.[Satish],
An Efficient VLSI Architecture for Template Matching Based on Moment Preserving Pattern Matching,
ICPR94(C:388-390).
IEEE DOI BibRef 9400

Tremblay, M., Savard, M., Poussart, D.,
Medium Level Scene Representation Using VLSI Smart Hexagonal Sensor with multi-resolution Edge Extraction Capability and Scale Space Integration Co-Processor,
CVPR94(632-637).
IEEE DOI BibRef 9400

Yates, R.B., Evans, S.J., Ivey, P.A.,
A 1.2 billion operations per second video signal processing chip,
ICIP94(III: 596-600).
IEEE DOI 9411
BibRef

Thacker, N.A., Courtney, P., Walker, S.N., Evans, S.J., Yates, R.B.,
Specification and design of a general purpose image processing chip,
ICPR94(C:268-273).
IEEE DOI 9410
BibRef

Stout, M.G., Salmon, L.G., Rudolph, G.L., Martinez, T.R.,
A VLSI implementation of a parallel, self-organizing learning model,
ICPR94(C:373-376).
IEEE DOI 9410
BibRef

Chen, S.[Sarit], Ginosar, R.,
Adaptive sensitivity CCD image sensor,
ICPR94(C:363-365).
IEEE DOI 9410
BibRef

Kabir, I., Hsieh, M., Donovan, W., Jabbi, A., Radke, W.,
Programmable image processing in a memory controller,
ICIP94(III: 672-677).
IEEE DOI 9411
BibRef

Tang, Y.Y., Cheng, X., Tao, L., Suen, C.Y., Talaat, M., Inglese, R.,
VLSI architecture for parallel concentration-contour approach,
ICPR92(IV:151-154).
IEEE DOI 9208
BibRef

Courtney, P.[Patrick], Thacker, N.A.[Neil A.], Brown, C.R.[Chris R.],
Hardware support for fast edge-based stereo,
ECCV92(902-906).
Springer DOI 9205
BibRef
And:
A Hardware Architecture for Image Rectification and Ground Plane Obstacle Detection,
ICPR92(IV:23-26).
IEEE DOI BibRef

Dron, L.,
System-level design of specialized VLSI hardware for computing relative orientation,
WACV92(128-135).
IEEE DOI 0403
BibRef

Patel, M., McCabe, P.A., Ranganathan, N.,
SIBA: a VLSI systolic array chip for image processing,
ICPR92(IV:15-18).
IEEE DOI 9208
BibRef

Sundaresan, V.K., Nichani, S., Ranganathan, N., Sankar, R.,
A VLSI hardware accelerator for dynamic time warping,
ICPR92(IV:27-30).
IEEE DOI 9208
BibRef

Botha, T.H.,
An analog CMOS programmable and configurable neural network,
ICPR92(IV:222-224).
IEEE DOI 9208
BibRef

Ishiyama, Y., Funaoka, C., Kubo, F., Takahashi, H., Tomita, F.,
Labeling board based on boundary tracking,
ICPR92(IV:34-38).
IEEE DOI 9208
Hardware implementation. BibRef

Fukushima, T.,
A survey of image processing LSIs in Japan,
ICPR90(II: 394-401).
IEEE DOI 9208
BibRef

Mao, W.D., Kung, S.Y.,
An object recognition system using stochastic knowledge source and VLSI parallel architecture,
ICPR90(I: 832-836).
IEEE DOI 9006
BibRef

Gijbels, T., van Eycken, L., Oosterlinck, A., Note, S., Catthoor, F.,
An ASIC-architecture for VLSI-implementation of the RBN-algorithm,
ICPR90(II: 408-412).
IEEE DOI 9208
BibRef

Chen, K., Astrom, A., Danielsson, P.E.,
PASIC: a smart sensor for computer vision,
ICPR90(II: 286-291).
IEEE DOI 9208
BibRef

Tremblay, M., Poussart, D.,
MAR: an integrated system for focal plane edge tracking with parallel analog processing and built-in primitives for image acquisition and analysis,
ICPR90(II: 292-298).
IEEE DOI 9208
BibRef

Klein, J.C., Collange, F., Bilodeau, M.,
A bit plane architecture for an image analysis processor implemented with P.L.C.A. gate array,
ECCV90(33-49).
Springer DOI 9004
BibRef

Chapter on Implementations and Applications, Databases, QBIC, Video Analysis, Hardware and Software, Inspection continues in
Hardware Implementations, FPGA, Image Processing .

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