20.2.11 Array Processors, Massive Parallel Systems, Pyramids

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Parallel Systems. Massive Parallel. Array Processors.

Fortes, J.A.B., Wah, B.W.,
Special Issue: Systolic Arrays-From Concept To Implementation,
Computer(20), No. 7, July 1987, pp. 12-103. BibRef 8707

Jagadish, H.V., Rao, S.K., Kailath, T.,
Array Architectures for Iterative Algorithms,
PIEEE(75), 1987, pp. 1304-1321. BibRef 8700

Fisher, A.L., Kung, H.T.,
Synchronizing Large VLSI Processor Arrays,
TC(34), 1985, pp. 734-740. BibRef 8500

Kung, H.T., Ruane, L.M., Yen, D.W.L.,
Two-Level Pipelined Systolic Array for Multidimensional Convolution,
IVC(1), No. 1, February 1983, pp. 30-36.
Elsevier DOI BibRef 8302

Kung, H.T.,
Systolic Algorithms for the CMU Warp Processor,
ICPR84(570-577). BibRef 8400

Fountain, T.J., Matthews, K.N., and Duff, M.J.B.,
The CLIP7A Image Processor,
PAMI(10), No. 3, May 1988, pp. 310-319.
IEEE DOI BibRef 8805

Fountain, T.J.,
The Development of the Clip7 Image Processing System,
PRL(1), 1983, pp. 331-379. BibRef 8300

Fountain, T.J., Postranecky, M., Shaw, G.K.,
The Clip4S System,
PRL(5), 1987, pp. 71-79. BibRef 8700

Duff, M.J.B.,
CLIP 4: A Large Scale Integrated Circuit Array Parallel Processor,
ICPR76(728-733). BibRef 7600

Duff, M.J.B., Watson, D.M., Fountain, T.J., Shaw, G.K.,
A Cellular Logic Array for Image Processing,
PR(5), No. 3, September 1973, pp. 229-240.
Elsevier DOI BibRef 7309

Fountain, T.J., Tomlinson, C.D.,
The Propagated Instruction Processor,
PDF File. 9509

Duff, M.J.B., Watson, D.M., Deutsch, E.S.,
A Parallel Computer for Array Processing,
IFIP74(94-97). BibRef 7400

Gerritsen, F.A.,
A Comparison of the CLIP4, DAP and MPP Processor-Array Implementations,
CSIP83(15-30). BibRef 8300

Kushner, T.R.[Todd R.], Wu, A.Y.[Angela Y.], and Rosenfeld, A.[Azriel],
Image Processing on MPP:1,
PR(15), No. 3, 1982, pp. 121-130.
Elsevier DOI The MPP is a 128X128 mesh connected array of processing elements that communicate by shifting 1 bit at a time. This paper discusses the relative times for the MPP and a VAX for a variety of operations. The ZMOB is also analyzed for the same operations. There may be a limit of N for any operation that requires propagation of data from one side to the other and nonregular' communication causes problems in the implementation. The speed ups are best for point operations and local area operations. BibRef 8200

Rosenfeld, A.[Azriel],
Parallel Image Processing Using Cellular Arrays,
Computer(16), No. 1, January 1983, pp. 14-20. Early work on CLIP. DAP, and MPP type machines. BibRef 8301

Ahuja, N., and Swamy, S.,
Multiprocessor Pyramid Architectures for Bottom-Up Image Analysis,
PAMI(6), No. 4, July 1984, pp. 463-475. Pyramid Structure. Organization of small processors for bottom-up analysis, in various pyramid schemes. Work done at Illinois CSL. BibRef 8407

Carpenter, G.A.[Gail A.], Grossberg, S.[Stephen],
A Massively Parallel Architecture for a Self-Organizing Neural Pattern Recognition Machine,
CVGIP(37), No. 1, January 1987, pp. 54-115.
Elsevier DOI BibRef 8701

Dixit, V., and Moldovan, D.I.,
Semantic Network Array Processor and Its Applications to Image Understanding,
PAMI(9), No. 1, January 1987, pp. 153-160. BibRef 8701
And: DARPA84(65-71). Similar to the following paper, but mostly on the architecture. BibRef

Dixit, V., Moldovan, D.I.,
Discrete Relaxation on Snap,
CAIA84(637-644). BibRef 8400

Moldovan, D.I., Wu, C.I., Nash, J.G., Levitan, S.P., and Weems, C.C.,
Parallel Processing of Iconic to Symbolic Transformation of Images,
CVPR85(257-264). Hardware, unclear how to use for vision. BibRef 8500

Young, T.Y., Liu, P.S.,
VLSI Array Architecture for Pattern Analysis and Image Processing,
HPRIP86(471-496). BibRef 8600

Reeves, A.P., and Rostampour, A.,
Computational Cost of Image Registration with a Parallel Binary Array Processor,
PAMI(4), No. 4, July 1982, pp. 449-455. BibRef 8207

Hwang, K.[Kai], Alnuweiri, H.M.[Hussein M.], Kumar, V.K.P.[V.K. Prasanna], Kim, D.S.[Dong-Seung],
Orthogonal Multiprocessor Sharing Memory with an Enhanced Mesh for Integrated Image Understanding,
CVGIP(53), No. 1, January 1991, pp. 31-45.
Elsevier DOI BibRef 9101

Basille, J.L.[Jean-Luc], Fernandez, P.[Pascal], Komen, E.R.[Erwin R.],
Recursive neighbourhood operations on the linear processor array SYMPATI-2,
IVC(10), No. 9, November 1992, pp. 625-630.
Elsevier DOI BibRef 9211

van der Wal, G.S., and Burt, P.J.,
A VLSI Pyramid Chip for Multiresolution Image Analysis,
IJCV(8), No. 3, 1992, pp. 177-189.
Springer DOI BibRef 9200

van der Wal, G.S.[Gooitzen S.],
Programmed implementation of real-time multiresolution signal processing apparatus,
US_Patent4,703,514, Oct 27, 1987
WWW Link. Pyramid implementation BibRef 8710

Burt, P.J.[Peter J.],
Pyramid processor for building large-area, high-resolution image by parts,
US_Patent4,797,942, 01/10/1989.
HTML Version. BibRef 8901

Burt, P.J.,
A pyramid-based front-end processor for dynamic vision applications,
PIEEE(90), No. 7, July 2002, pp. 1188-1200.

van der Wal, G.S.[Gooitzen S.],
Pyramid processor integrated circuit,
US_Patent5,359,674, 10/25/1994,
HTML Version. BibRef 9410

Bassman, R.G.[Robert G.], Bhatt, B.B.[Bhavesh B.], Call, B.J.[Bill J.], Hansen, M.W.[Michael W.], Hsu, S.C.[Stephen C.], van der Wal, G.S.[Gooitzen S.], Wixson, L.E.[Lambert E.],
Parallel-pipelined image processing system,
US_Patent6,044,166, 03/28/2000.
HTML Version. More pyramid machines. BibRef 0003

Nudd, G.R., Francis, N.D., Atherton, T.J., Kerbyson, D.J., Packwood, R.A., Vaudin, G.J.,
Hierarchical Multiple-SIMD Architecture for Image Analysis,
MVA(5), 1992, pp. 85-103. BibRef 9200
Earlier: A1, A3, A2, Add Howarth, R.M., A4, A5, A6: ICPR90(II: 642-647).

Franics, N.D., Nudd, G.R., Atherton, T.J., Kerbyson, D.J., Packwood, R.A., Vaudin, J.,
Performance evaluation of the hierarchical Hough transform on an associative M-SIMD architecture,
ICPR90(II: 509-511).

Nudd, G.R., Atherton, T.J., Kerbyson, D.J.,
An heterogeneous M-SIMD architecture for Kalman filter controlled processing of image sequences,

Nash, J.G., Etchells, R.D., Grinberg, J., Hansen, S., Little, M.J., Nudd, G.R., Petrozolin, K., Turk, R.,
VLSI Implementation of Systolic and 3-D Cellular Architectures for Image Processing,
DARPA84(56-64). Hughes Research Labs. BibRef 8400

Biancardi, A., Cantoni, V., Mosconi, M.,
Program Development and Coding on a Fine-Grained Vision Machine,
MVA(7), 1993, pp. 23-29. BibRef 9300

Biancardi, A., Mosconi, M.,
Visual debugging for a pyramidal machine,

Cantoni, V.[Virginio], and Ferretti, M.[Marco],
Pyramidal Architectures for Computer Vision,
PlenumPublishing, 1994, 331 pp. ISBN 0-306-44453-4/331. Hierarchical structures, architectures, language support, algorithms, applications. BibRef 9400

Cantoni, V., Lombardi, L., Ferretti, M.,
Hierarchical multi-microcomputer systems,
ICPR90(II: 476-478).

Shoari, S., Kavianpour, A., Bagherzadeh, N.,
Pyramid Simulation of Image-Processing Applications,
IVC(12), No. 8, October 1994, pp. 523-529.
Elsevier DOI BibRef 9410

Fujita, Y., Yamashita, N., Okazaki, S.,
A Real-Time Vision System Using an Integrated Memory Array Processor Prototype,
MVA(7), No. 4, 1994, pp. 220-228. BibRef 9400

Yamashita, N., Fujita, Y., Okazaki, S.,
An Integrated Memory Array Processor with a Synchronous-DRAM Interface for Real-Time Vision Applications,
ICPR96(IV: 575-580).
(NEC Corporation, J) BibRef

Okazaki, S., Fujita, Y., Yamashita, N.,
A compact real-time vision system using integrated memory array processor architecture,
CirSysVideo(5), No. 5, October 1995, pp. 446-452.
IEEE Top Reference. 0206

Pissaloux, E.E., Bonnin, P.,
On the Evolution of Parallel Computers Dedicated to Image-Processing Through Examples of Some French Computers,
DSP(7), No. 1, January 1997, pp. 13-27. 9703

Pissaloux, E.E.,
An Adaptive Parallel System Dedicated to Projective Image Matching,
ICIP00(Vol II: 507-510).

Pissaloux, E.E.[Edwige E.], Le Coat, F.[Francois], Bonnin, P.[Patrick], Tissot, A., Durbin, F.,
Design and Optimization of a Parallel Architecture Dedicated to Image Matching,
IEEE DOI BibRef 9900

Le Coat, F., Pissaloux, E.E., Bonnin, P., Garie, T., Durbin, F., Tissot, A.,
A Parallel Algorithm for a Very Fast 2D Velocity Field Estimation,
ICIP97(II: 179-182).
IEEE DOI BibRef 9700

Pissaloux, E.E., Le Coat, F., Bonnin, P., Tissot, A., Durbin, F., Garie, T.,
Design and Realisation of a Parallel Systolic Architecture Dedicated to Aerial Image Matching,
MVA98(xx-yy). BibRef 9800

Diamantaras, K.I., Kung, S.Y.,
A Linear Systolic Array for Real Time Morphological Image Processing,
VLSIVideo(17), No. 1, September 1997, pp. 43-55. 9711

Guerra, C.,
2D Object Recognition on a Reconfigurable Mesh,
PR(31), No. 1, January 1998, pp. 83-88.
Elsevier DOI 9802

Wallace, A.M., Michaelson, G.J., Scaife, N.R., Austin, W.J.,
A Dual Source, Parallel Architecture for Computer Vision,
Super(12), No. 1-2, 1998, pp. 37-56. 9805

Scaife, N.R., Michaelson, G.J., Wallace, A.M.,
Prototyping Parallel Algorithms using Standard ML,
PDF File. 9509

Chung, Y.W.[Yong-Wha], Prasanna, V.K.[Viktor K.],
Parallelizing Image Feature Extraction on Coarse-Grain Machines,
PAMI(20), No. 12, December 1998, pp. 1389-1394.
IEEE DOI MIMD Speedups of 27+ on 32 and 56 on 64 processors. BibRef 9812

Chung, Y., Choi, S., and Prasanna, V.K.,
Parallel Object Recognition on an FPGA-based Configurable Computing Platform,
CAMP97(Session 5). BibRef 9700

Chung, Y., Prasanna, V.K., Wang, C.L.,
Parallel Algorithms for Linear Approximation on Distributed Memory Machines,
ARPA96(1465-1472). BibRef 9600
A Fast Asynchronous Algorithm for Linear Feature Extraction on IBM SP-2,
CAMP95(xx). Extracting linear features. BibRef

Balsara, P.T., Irwin, M.J.,
Intermediate-level vision tasks on a memory array architecture,
MVA(6), No. 1, 1993, pp. 50-65. BibRef 9300

Soldek, J.[Jerzy], Mantiuk, R.[Radoslaw],
A reconfigurable processor based on FPGAs for pattern recognition, processing, analysis and synthesis of images,
PRL(20), No. 7, July 1999, pp. 667-674. BibRef 9907

Meribout, M.[Mahmoud], Nakanishi, M.[Mamoru], Ogura, T.[Takeshi],
A Real-Time Image Segmentation on a Massively Parallel Architecture,
RealTimeImg(5), No. 4, August 1999, pp. 279-291. BibRef 9908

Mukai, T.[Toshiharu], Ohnishi, N.[Noboru],
A robust eigenspace method for obtaining feature values in high-speed massively parallel vision systems,
MVA(12), No. 4, 2000, pp. 197-202.
Springer DOI 0101

Zhao, D., Daut, D.G.,
A real-time column array processor architecture for images,
CirSysVideo(2), No. 1, March 1992, pp. 38-48.
IEEE Top Reference. 0206

Rabah, H., Mathias, H., Weber, S., Mozef, E., Tanougast, C.,
Linear array processors with multiple access modes memory for real-time image processing,
RealTimeImg(9), No. 3, June 2003, pp. 205-213.
Elsevier DOI 0310

Chao, W.M., Chen, L.G.,
Pyramid Architecture for 3840 X 2160 Quad Full High Definition 30 Frames/s Video Acquisition,
CirSysVideo(20), No. 11, November 2010, pp. 1499-1508.

Liu, C.L., Vaidyanathan, P.P.,
Remarks on the Spatial Smoothing Step in Coarray MUSIC,
SPLetters(22), No. 9, September 2015, pp. 1438-1442.
Array signal processing. Multiple Signal Classification. BibRef

Zhu, X.N.[Xiao-Ning], Meng, Q.Y.[Qing-Yue], Gu, L.Z.[Li-Ze],
Real-time image recognition using weighted spatial pyramid networks,
RealTimeIP(14), No. 3, October 2018, pp. 617-629.
WWW Link. 1811

Xiao, G.[Guoyao], Quan, Y.H.[Ying-Hui], Sun, Z.Z.[Zong-Zheng], Wen, B.[Bo], Liao, G.S.[Gui-Sheng],
Design of a Digital Array Signal Processing System with Full Array Element,
RS(15), No. 16, 2023, pp. 4043.
DOI Link 2309

Zamanlooy, B.[Babak], Vaghef, V.H.[Vahid Hamiati], Mirzakuchaki, S.[Sattar], Bakhtiari, A.S.[Ali Shojaee], Atani, R.E.[Reza Ebrahimi],
A Real Time Infrared Imaging System Based on DSP and FPGA,
Springer DOI 0712

Kiryukhin, G., Celenk, M.,
Implementation of 2D-DCT on XC4000 Series FPGA Using DFT-based DSFG and DA Architectures,
ICIP01(III: 302-305).

vander Molen, M., Jonker, P.P.,
A Comparison of Linear Processor Arrays for Image Processing,
MVA98(xx-yy). BibRef 9800

Chalermwat, P., Alexandridis, N.A., Piamsa-Nga, P., O'Connell, M.,
Parallel image processing in heterogeneous computing network systems,
ICIP96(II: 161-164).

Alnuweiri, H.M., Prasanna Kumar, V.K.,
Optimal Geometric Algorithms on Fixed-Size Linear Arrays and Scan Line Arrays,
IEEE DOI BibRef 8800

Gealow, J.C., Love, N.S., Hall, G., Masaki, I., Sodini, C.G.,
Desktop Programmable Pixel-Parallel Accelerator for High Speed Image Processing,
DARPA97(1379-1384). BibRef 9700

Eshaghian, M.M., Prasanna-Kumar, V.K.,
Fine Grain Image Computations on Electro-Optical Arrays,
IEEE DOI BibRef 8900

Ignatiev, V.M.[Virgily Michailovich], Abuzova, I.V.[Irina Virgilievna], and Larkin, E.V.[Eugene Vasilyevich],
On Time Aspects of an Image Processing in MIMD Computers,
HTML Version. 9705

Duclos, P., Boeri, F., Auguin, M., Giraudon, G.,
Image processing on a SIMD/SPMD architecture: OPSILA,
ICPR88(I: 430-433).

Blanford, R.P., and Tanimoto, S.L.,
A Pyramid Machine Simulator for the Symbolics 3600,
CVPR86(427-429). Simulate the machine before building it. BibRef 8600

Stofo, S.J., Miranker, D., Shaw, D.E.,
Architecture and Applications of DADO: A Large-Scale Parallel Computer for Artificial Intelligence,
IJCAI83(850-854). BibRef 8300

Chapter on Implementations and Applications, Databases, QBIC, Video Analysis, Hardware and Software, Inspection continues in
Hardware -- Image Understanding Architecture, IUA .

Last update:Jun 17, 2024 at 21:38:11