Journals starting with dasi

DASIP14 * *Design and Architectures for Signal and Image Processing
* Review of World's Fastest Connected Component Labeling Algorithms: Speed and Energy Estimation, A

DASIP15 * *Design and Architectures for Signal and Image Processing
* *MATIP: A dynamic hardware task integration platform for Multiprocessing Reconfigurable System on Chip
* BM3D image denoising using heterogeneous computing platforms
* Compa backend: A dynamic runtime for the execution of dataflow programs onto multi-core platforms
* Demonstrating an FPGA implementation of a full HD real-time HEVC decoder with memory optimizations for range extensions support
* Dynamic power evaluation of LTE wireless baseband processing on FPGA
* Evaluation of analog and digital signal processing on PSoC architecture with DCT as use case: Comparison of an analog and software based implementation of the digital cosine transform on a Programmable System on Chip
* Exploring custom heterogeneous MPSoCs for real-time neural signal decoding
* Exploring the concurrent execution of HEVC intra encoding algorithms for heterogeneous multi core architectures
* Fast and accurate power estimation for application-specific instruction set processors using FPGA emulation
* Fast and efficient signals recovery for deterministic compressive sensing: Applications to biosignals
* FPGA based system for real-time structure from motion computation
* FPGA implementations of HEVC Inverse DCT using high-level synthesis
* FPGA-based detection of QRS complexes in ECG signal
* FPGA-based real-time MFCC extraction for automatic audio indexing on FM broadcast data
* Hardware implementation of a soft cancellation decoder for polar codes
* Image tiling for embedded applications with non-linear constraints
* Implementation of a Fast Fourier transform algorithm onto a manycore processor
* Implementation of IEEE-802.11a/g receiver blocks on a coarse-grained reconfigurable array
* Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding
* Real-time correlation for locating systems utilizing heterogeneous computing architectures
* Reducing the impact of internal upsets inside the correlation process in GPS Receivers
* Reliable NCO carrier generators for GPS receivers
* Robot navigation based on an efficient combination of an extended A* algorithm, bird's eye view and image stitching
* Selecting most profitable instruction-set extensions using ant colony heuristic
* Worst-case latency analysis of SDF-based parametrized dataflow MoCs
26 for DASIP15

DASIP16 * *Design and Architectures for Signal and Image Processing
* Analysis on scalability and energy efficiency of HEVC decoding using task-based programming model
* ARM-FPGA based platform for automated adaptive wireless communication systems using partial reconfiguration technique
* Associative Memory based on clustered Neural Networks: Improved model and architecture for Oriented Edge Detection
* Batched Cholesky factorization for tiny matrices
* Code generation for a SIMD architecture with custom memory organisation
* comparison of cost construction methods onto a C6678 platform for stereo matching, A
* Crosstalk-aware link power model for Networks-on-Chip
* Custom processor design for efficient, yet flexible Lucas-Kanade optical flow
* dedicated lightweight binocular stereo system for real-time depth-map generation, A
* Demo abstract: FPGA-based implementation of a flexible FFT dedicated to LTE standard
* Demo abstract: How fuzzy logic can enhance energy management in Wireless Sensor nodes equipped by energy harvesters and wake-up radios
* Demo: Efficient delay and apodization for on-FPGA 3D ultrasound
* Demo: HELICoiD tool demonstrator for real-time brain cancer detection
* Demo: Ker-ONE: Embedded virtualization approach with dynamic reconfigurable accelerators management
* Demo: Localisation in a faulty digital GPS receiver
* Demo: MPPA: manycore processor towards future ADAS system solutions
* Demo: Overlay architectures for heterogeneous FPGA cluster management
* Demo: Reconfigurable Platform Composer Tool
* Demo: SLP-aware word length optimization
* Demo: UHD live video streaming with a real-time scalable HEVC encoder
* Efficient parallel architecture of an intra-only scalable multi-layer HEVC encoder
* ELM-based hyperspectral imagery processor for onboard real-time classification
* Estimating encoding complexity of a real-time embedded software HEVC codec
* FPGA memory optimization for real-time imaging
* FPGA-based bio-inspired architecture for multi-scale attentional vision
* FPGA-based Hardware-in-the-Loop environment using video injection concept for camera-based systems in automotive applications
* Fuzzy logic modeling for objective image quality assessment
* Generation of schedule tables on multi-core systems for AUTOSAR applications
* Hardware acceleration of Maximum-Likelihood angle estimation for automotive MIMO radars
* Hardware architecture for lowering the error floor of LTE turbo codes
* Hyperspectral image classification using a parallel implementation of the linear SVM on a Massively Parallel Processor Array (MPPA) platform
* Low power design methodology for signal processing systems using lightweight dataflow techniques
* Memory efficient Multi-Scale Line Detector architecture for retinal blood vessel segmentation
* Memory management in embedded vision systems: Optimization problems and solution methods
* Monte Carlo method based precision analysis of deep convolution nets
* pipelined multi-softcore approach for the HOG algorithm, A
* Scalable HEVC decoder for mobile devices: Trade-off between energy consumption and quality
* system-level security approach for heterogeneous MPSoCs, A
* SystemC modelling of lossless compression IP cores for space applications
40 for DASIP16

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